Field
Embodiments of the present invention generally relate to integrated circuit analysis techniques and, more particularly, a method and apparatus for conducting automated integrated circuit analysis.
Description of the Related Art
Modern integrated circuits are very complex. When an integrated circuit fails, or if it does not function as expected, isolating the reason for failure of the integrated circuit is very challenging. Often, large amounts of design information are used to trace the origin of a failure to physical device characteristics that lead to the failure. Once that is accomplished, local analysis of the devices may be possible to perform using standard probing tools. One of these tools often uses laser probing techniques with laser scanning microscopes. When using laser probes, it is necessary to navigate to a specific region of an integrated circuit with the help of the design information (usually in the form of a netlist or layout schematic) to noninvasively measure electronic waveforms (either the RMS power or the actual time-dependent waveform), and determine if that waveform is anomalous or not. These tools are often used by highly trained technicians who manually navigate around the device and collect waveforms. The technicians then compare the waveforms to simulations to determine if there was an error. Such manual analysis is time consuming and costly. Moreover, these methods are restricted to devices where a significant amount of design knowledge is available to the technicians. In cases where the design is not known, it is necessary to destructively reverse engineer the device to determine the design prior to performing analysis of the functionality. Destructive reverse engineering processes are undesirable, because they leave the device in a non-functioning state. In some instances, it is possible to combine the destructive reverse engineering step with standard laser probing to identify the design of the IC, however successful alignment of data from electron microscopes and laser probing microscopes requires manual user input.
There is a highly varying degree of device geometry visibility between idealized layout files, electron microscope images, and optical images. In particular, integrated circuits that are manufactured by third parties may contain features that are smaller than the diffraction limited spot size of the imaging system. In those cases, little design information is known and standard recognition methods are not effective because the unaided imaging system cannot resolve sufficiently detailed images to accurately recognize logic elements in the integrated circuit. Moreover, geometry alone is an insufficient parameter for device analysis. Standard destructive methods that focus only on geometric details are unable to efficiently detect process-related deficiencies that are intermittent or caused by device stress due to heat, age or other physical causes
Therefore, there is a need in the art to develop generalized device analysis methods that can automatically identify and isolate faults, even when full device design information is unavailable.